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d a t a sh eet objective speci?cation file under integrated circuits, ic02 2000 may 19 integrated circuits TDA8961 atsc digital terrestrial tv demodulator/decoder
2000 may 19 2 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 features general features one-chip atsc-compliant demodulator and concatenated trellis (viterbi)/reed solomon decoder with de-interleaver and de-randomizer 0.35 m m process 3.3 v device qfp80 package boundary scan test (bst) 12 mhz external clock 36 mhz output for external d/a converter parallel or serial mpeg-2 transport stream output. 8-vestigial side band (vsb) demodulator accepts 10-bit if data sampled at 36 mhz 6 mhz wide if signal, centered at 4 mhz on-chip digital circuitry for tuner agc square-root raised-cosine filter with 11.5% roll-off factor fully internal carrier recovery loop no need for external voltage controlled crystal oscillator due to internal sample rate converter fully internal symbol timing recovery with programmable loop filters technology to handle dynamic multipath conditions. adaptive equalizer including feed forward and feedback sections with decision feedback equalizer (dfe) structure range of - 2.3 to +22.5 m s by default (in conjunction with external software, - 2.3 to +80 m s) adaptation based on atsc field sync (trained) and/or 8-vsb data (blind). ntsc co-channel interference ?lter patented ntsc co-channel interference technology with low noise penalty. on-chip forward error correction trellis (viterbi) decoder rate 2 3 (rate 1 2 ungerboeck code based) (207, 187, t = 10) reed solomon code internal convolutional de-interleaving (i = 52; using internal memory) external indication of uncorrectable error; transport_error_indicator bit in mpeg packet header is also set de-randomizer based on atsc standard segment error rate readable through i 2 c. i 2 c interface i 2 c-bus interface to initialize and monitor the demodulator and forward error correction (fec) decoder. an operation without i 2 c-bus is possible (default). system interfaces 8-bit wide or serial mpeg-2 transport stream interface itu656 bypass mode mpeg-2 serial transport stream input to reduce external components when the ic is combined in a system with a quadrature amplitude modulation (qam), quadrature phase shift keying (qpsk) or orthogonal frequency division multiplexing (ofdm) channel decoder. applications digital atsc compliant tv receiver personal computers with digital television capabilities set top-boxes. ordering information type number package name description version TDA8961 qfp80 plastic quad ?at package; 80 leads (lead length 1.95 mm); body14 20 2.8 mm sot318-2
2000 may 19 3 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 general description the TDA8961 is an advanced television systems committee (atsc)-compliant demodulator and fec decoder for reception of 8-vsb modulated signals for terrestrial and cable applications: terrestrial: reception of 8-vsb modulated signals via standard 6 mhz vhf/uhf terrestrial tv channels (tv channels 2 to 69 in the united states). cable: reception of 8-vsb modulated signals via standard 6 mhz vhf/uhf cable tv channels. an application using the TDA8961 and the tda8980 ntsc/atsc tv input processor for tv and multi-media is shown in fig.1. a tuner converts the incoming rf signal to a fixed if centered at 44 mhz. the output signal from the tuner is filtered and fed to the tda8980 which performs the following functions: decodes the analog ntsc signals: the audio signals are digitized, using on-chip audio stereo a/d converters, into an i 2 s-bus stream; the video information is digitized, using on-chip video a/d converters, into an itu656 stream. down converts the incoming 6 mhz wide 8-vsb if signal to a low-if signal centered at 4 mhz: the low-if signal is then digitized, using an on-chip 10-bit a/d converter, and fed to the TDA8961 for further processing. in this application, agc is also managed by the tda8980 so that no other external components, such as an operational amplifier loop integrator, are required. although the tda8980 has an internal 2-d comb filter, external filters such as a 3-d comb filter and other picture improvement devices can easily be connected. sound can be decoded using an external device such as the tda9851 i 2 c-bus controlled economic btsc stereo decoder. this ic has an internal switch allowing it to process either analog ntsc if or digital 8-vsb if signals. a 12 mhz clock signal is generated using a 12 mhz crystal connected to the tda8980. the TDA8961 also uses this clock signal which is fed from the tda8980 to pin xtali of the TDA8961. handbook, full pagewidth adclk adin9 to adin0 TDA8961 tda8980 xtali agcout pdoerr pdoval pdo7 to pdo0 pdosync pdoclk vclk d9 to d0 ref12m tvifin vsbifin tuneragc vifagc x12min 12 mhz x12mout pdi0 pdisync pdival serial mpeg-2 transport stream input mpeg-2 transport stream pdiclk pdierr ntsc saw filter tuner flat saw filter i 2 c i 2 c i 2 c master i 2 c mgu085 fig.1 front-end design for a hybrid tv system using the tda8980 and TDA8961.
2000 may 19 4 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 the incoming data has a sample rate of 36 mhz. this is internally converted to a sample rate of 21.52 mhz which is twice the 8-vsb symbol rate. this patented philips semiconductors technology eliminates the need for external symbol timing recovery loop components. when the tda8980 is decoding analog ntsc, the TDA8961 can be set to a itu656 bypass mode which allows the 8-bit itu656 data output from the tda8980 to appear at the TDA8961 moving pictures expert group (mpeg-2) transport stream output, from where it can be fed to the main graphics display device in the system. the recovery of the carrier is performed entirely within the TDA8961. this function consists of a digital frequency and frequency phase-locked loop (fpll). data shaping is performed by a square-root raised-cosine (half nyquist) filter having a roll-off factor of 11.5%. after the TDA8961 has performed carrier recovery, nyquist filtering and symbol timing recovery, it then performs adaptive equalization. the adaptive equalizer uses a dfe structure with equalization based on the atsc field sync (trained equalization) and/or the 8-vsb data itself (blind equalization). the equalizer is followed by a patented ntsc co-channel interference filter which removes any unwanted ntsc signal interference from the 8-vsb terrestrial dtv signal. after trellis decoding, the stream is de-interleaved to a depth of 52 by a convolutional de-interleaver whose memory is provided on-chip. the reed solomon decoder is atsc-compliant, with a length of 207, and able to correct up to 10 bytes. the decoded stream is then de-randomized using a pseudo-random binary sequence (prbs) and the data passed to a fifo which prevents the appearance of irregular gaps in the output data. the output of the TDA8961 is a clock signal and an atsc-compliant mpeg-2 packetized data stream. signal flag outputs are provided to indicate the occurrence of sync bytes, valid data bytes and uncorrected reed solomon blocks. the packetized data stream is available in either an 8-bit parallel, or a 1-bit serial format for connection to an mpeg-2 transport stream demultiplexer. an application using the TDA8961 and a stand-alone tda9829 downconverter for dvb (digital video broadcast) with an a/d converter is shown in fig.2. a tuner converts the incoming rf signal to a fixed if centered at 44 mhz. the output signal from the tuner is filtered using two surface acoustical wave (saw) filters and then down converted to an if of 4 mhz by the tda9829. the signal is then digitized by an a/d converter at a sample rate of 36 mhz using the clock signal output from the TDA8961. the full input range of the a/d converter is utilized by placing it within what is effectively a fine-agc loop integrator circuit which has a variable gain stage at the output of the if downmixer section. however, it is also possible to apply the agc control output of the TDA8961 to the tuner via the integrator. the peak level of the input signals to the TDA8961 is determined by the agc output detector which is located just after the a/d. handbook, full pagewidth tda9829 if downmixer TDA8961 v odvb rf v iif v ref clk36 adclk adin9 to adin0 mpeg-2 transport stream pdo7 to pdo0 v agc integrator agcout agc 44 mhz 96 mhz tuner rf vco 12 mhz xtali saw filter oscillator ? 8 a d mgu086 saw filter fig.2 front-end design for the TDA8961 using a stand-alone if down converter (tda9829) and a/d converter.
2000 may 19 5 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 quick reference data note 1. corresponds to 12 training sequences. symbol parameter conditions min. typ. max. unit v dd supply voltage 2.7 3.3 3.6 v i dd supply current v dd = 3.3 v - 390 - ma f clk clock frequency - 12 - mhz f sym symbol frequency - 10.76 - msymbols/s f s sample frequency - 36 - mhz f c(if2) second if centre frequency - 4 - mhz il implementation loss --- db a ro half nyquist ?lter roll-off factor - 11.5 - % t acq acquisition time note 1 -- 290 ms t amb ambient temperature - 20 - +70 c p tot total power dissipation - 1.3 - w
2000 may 19 6 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 block diagram handbook, full pagewidth digital front-end: * sample rate converter * fine agc * carrier recovery * half nyquist filtering * sync recovery and pilot removal * symbol timing recovery * adaptive equalization ntsc co-channel interface filter trellis decoder de-interleaver reed solomon decoder de-randomizer clock generation i 2 c-bus interface control tms adin9 to adin0 adclk tdo tdi trst tck lockindic eqlockindic rst_an a0 a1 scl sda pdisync pdiclk pdierr pdival pdi0 xtali xtalo clk36 boundary scan test controller output formatter 39 40 43, 44, 45, 47, 48, 49, 51, 52 37 41 27 28 32 30 26 75 70 69 16 15 14 13 77 79 78 21 22 19 23 20 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 80 66 pdosync TDA8961 pdoclk pdo7 to pdo0 pdoval pdoerr 34 fsync 35 ssync 67 fshndshk agcout mgu087 fig.3 block diagram.
2000 may 19 7 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 pinning symbol pin i/o description adin0 1 i data input bit 0 (lsb) adin1 2 i data input bit 1 adin2 3 i data input bit 2 adin3 4 i data input bit 3 adin4 5 i data input bit 4 adin5 6 i data input bit 5 adin6 7 i data input bit 6 adin7 8 i data input bit 7 adin8 9 i data input bit 8 adin9 10 i data input bit 9 (msb) v ddd1 11 - digital core supply voltage 1 (3.3 v) v ssd1 12 - digital core ground 1 a0 13 i i 2 c-bus slave address bit 0 a1 14 i i 2 c-bus slave address bit 1 scl 15 i i 2 c-bus clock sda 16 i/o i 2 c-bus serial data v ddd2 17 - i/o supply (3.3 v) v ssd2 18 - digital core ground 2 tdi 19 i tap controller data input; note 1 tms 20 i tap controller test mode select; note 1 tck 21 i tap controller test clock; note 1 trst 22 i tap controller asynchronous reset (active low); notes 1 and 2 tdo 23 o tap controller test data (3-state); note 1 v ddd3 24 - digital core supply voltage 3 (3.3 v) v ssd3 25 - digital core ground 3 pdisync 26 i transport stream interface packet sync indicator pdi0 27 i transport stream interface packet data bit 0 pdival 28 i transport stream interface packet data valid signal v ddd4 29 - digital core supply voltage 4 (3.3 v) pdiclk 30 i transport stream interface packet data clock signal v ssd4 31 - digital core ground 4 pdierr 32 i transport stream interface packet error signal v ddd5 33 - digital core supply voltage 5 (3.3 v) fsync 34 i ?eld sync strobe (for debug modes) ssync 35 i segment sync strobe (for debug modes) v ssd5 36 - digital core ground 5 pdoerr 37 o transport stream interface packet error signal (3-state) v ddq1 38 - i/o supply voltage 1 (3.3 v) pdosync 39 o transport stream interface packet sync indicator signal (3-state) pdoval 40 o transport stream interface packet data valid indicator signal (3-state)
2000 may 19 8 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 pdoclk 41 o transport stream interface packet data clock signal (3-state) v ssq1 42 - i/o ground 1 pdo7 43 o transport stream interface packet data bit 7 (3-state) pdo6 44 o transport stream interface packet data bit 6 (3-state) pdo5 45 o transport stream interface packet data bit 5 (3-state) v ddq2 46 - i/o supply voltage 2 (3.3 v) pdo4 47 o transport stream interface packet data bit 4 (3-state) pdo3 48 o transport stream interface packet data bit 3 (3-state) pdo2 49 o transport stream interface packet data bit 2 (3-state) v ssq2 50 - i/o ground 2 pdo1 51 o transport stream interface packet data bit 1(3-state) pdo0 52 o transport stream interface packet data bit 0 (3-state) v ddq3 53 - i/o supply 3 (3.3 v) n.c. 54 not connected n.c. 55 not connected v ssq3 56 - i/o ground 3 n.c. 57 not connected n.c. 58 not connected n.c. 59 not connected v ddq4 60 - i/o supply 4 (3.3 v) n.c. 61 not connected n.c. 62 not connected n.c. 63 not connected v ssq4 64 - i/o ground 4 n.c. 65 not connected agcout 66 o agc control (3-state) fshndshk 67 o ?eld sync strobe or symbol capture memory handshake signal v dda1 68 - analog supply voltage (3.3 v) xtali 69 i external crystal xtalo 70 o external crystal v ssa1 71 - analog ground 1 v dda2 72 - analog supply 2 (3.3 v) n.c. 73 not connected v ddq5 74 - i/o supply 5 (3.3 v) clk36 75 o 36 mhz clock signal v ssq5 76 - i/o ground 5 rst_an 77 i asynchronous reset (active low) lockindic 78 o front-end lock indicator eqlockindic 79 o equalizer lock indicator adclk 80 i incoming data sampling clock signal (36 mhz) symbol pin i/o description
2000 may 19 9 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 notes 1. input pins tck, tdi, tms and trst have an internal pull-up transistor and must be connected to ground when not used; pin tdo is a 3-state output in accordance with ieee 1149.1. 2. pin trst is active low. it can be used to immediately force the test access port (tap) controller to the test logic reset state (normal operation) in accordance with ieee 1149.1.
2000 may 19 10 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 handbook, full pagewidth TDA8961 mgu088 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 adin0 adin1 adin2 adin3 adin4 adin5 adin6 adin7 adin8 adin9 v ddd1 v ssd1 a0 a1 scl sda v ddd2 v ssd2 tdi tms tck trst tdo v ddd3 v ssq4 n.c. n.c. n.c. v ddq4 n.c. n.c. n.c. v ssq3 n.c. n.c. v ddq3 pdo0 pdo1 v ssq2 pdo2 pdo3 pdo4 v ddq2 pdo5 pdo6 pdo7 v ssq1 pdoclk 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 adclk eqlockindic lockindic rst_an v ssq5 clk36 v ddq5 n.c. v dda2 v ssa1 xtalo xtali v dda1 fshndshk agcout n.c. v ssd3 pdisync pdi0 pdival v ddd4 pdiclk v ssd4 pdierr v ddd5 fsync ssync v ssd5 pdoerr v ddq1 pdosync pdoval fig.4 pin configuration.
2000 may 19 11 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 functional description the internal architecture of the TDA8961 basically comprises two parts: the front-end: containing the agc, carrier recovery, half nyquist filter, symbol timing recovery, sync recovery and adaptive equalization sections. the back-end: containing the ntsc co-channel rejection filter, trellis decoder, de-interleaver, the reed solomon decoder and de-randomizer sections. sample rate converter i ntroduction the sample rate converter section changes the incoming data frequency of 36 mhz to an internal sampling frequency of twice the symbol rate. the 10-bit wide data from either the tda8980 or a stand-alone a/d converter (tda8763a is recommended) arrives at the sample rate converter input of the TDA8961 via inputs adin9 to adin0. the format of the incoming samples can be programmed by the status of i 2 c-bus bit ad_fmt (see table 9). the format can be either twos complement or binary. the default setting is binary to comply with the tda8980. p inning the functions of the input interface pins are given in table 1. if a stand-alone a/d converter is used, pin clk36 is connected externally to pin adclk. fine agc the fine agc section controls the gain of analog signals over a range of 20 db. the level of the signal at pins adin9 to adin0 is monitored and an average level from several samples is acquired. the default number of samples is 64, but this value can be set to 256 by setting i 2 c-bus bit agc_samples (see table 10). a comparator compares the level of the filtered signal with a threshold level represented by a signed four-bit value set by i 2 c-bus bits agc_tr_low. the comparator output determines the level at pin agcout which is used to either charge or discharge an off-chip ideal integrator, which in turn, controls the gain of the tuner front-end module. to make the level at pin agcout compatible with the agc circuits in other devices, the comparator output can be inverted by setting i 2 c-bus bit agc_dir (see table 10). the default value of bit agc_dir is 0 making the output at pin agcout compatible with the agc circuit in the tda8980. the levels at pin agcout with respect to the value of bit agc_dir are shown in table 2. the agc section can be reset by setting i 2 c-bus bit agc_reset (see table 8). table 1 input interface table 2 agc name function adin9 to adin0 10-bit data input (from external a/d converter) adclk 36 mhz clock signal input clk36 clock signal output for sampling incoming data (to external a/d converter) filter output level comparator output i 2 c-bus bit agc_dir pin agcout above threshold 1 0 1 below threshold 0 0 0 above threshold 1 1 0 below threshold 0 1 1 equal to threshold z 0 z
2000 may 19 12 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 carrier recovery the carrier recovery circuit recovers the frequency and phase of the pilot carrier signal. if, as in some cases, the pilot signal is present at the higher edge of the vsb spectrum, the i 2 c-bus bit cr_inv can be set to ensure that when the frequency is shifted, the pilot signal is dc. half nyquist ?ltering the half nyquist filtering section is a square-root raised-cosine filter with 11.5% roll-off. sync recovery the sync recovery section performs several functions including the recovery of segment sync and field sync. when this section detects the data segment sync signal, pin lockindic goes high. the status of pin lockindic can also be read via the i 2 c-bus bit lock_indicator (see table 16). timing recovery the timing recovery section takes signals from the half nyquist filter and forms part of a closed loop in order to acquire and maintain a constant sampling rate and clock frequency for the complete system. adaptive equalizer the adaptive equalizer comprises a forward filter and a feedback filter section. at every symbol period, it receives demodulated symbols from the sync recovery section. the equalizer filters these symbols in an attempt to eliminate the effects of multipath conditions on the symbol stream during transmission. the coefficients of the filters are updated every symbol period using the training sequence and/or using blind equalization if required. the equalizer is designed to correct a maximum pre-echo of 2.32 m s and a maximum post-echo of 22.5 m s. the equalizer has an optimized typical acquisition time of 12 training sequences, which corresponds to about 290 ms. it is defined that acquisition occurs when the output signal-to-noise ratio reaches the threshold of visibility (tov). for 8-vsb, the atsc defines a tov of 14.9 db. a mean square error (mse) signal is generated based on the training signal and on the output of the equalizer. the error signal represents a 16-bit value which is read via the i 2 c-bus bit mse (see table 18) and used to monitor the channel adaptation process. it is possible to use software control to extend the range of the feedback filter to a maximum of 80 m s. c ontrol an integrated sophisticated finite state machine controls the sequence of operations that must be performed to correctly decode a valid vsb data signal into an mpeg-2 packetized transport stream. after a reset has been applied, the finite state machine is in state 0. when a valid vsb data signal is detected, the finite state machine ensures that the following three states occur. state 1: channel acquisition in this state there is either no channel signal present or a channel signal is in the process of being acquired. before the channel signal can be acquired, the agc, timing recovery and carrier recovery loops must first lock onto it. if segment sync lock is lost, either pin lockindic goes low, or a hardware reset is applied to the TDA8961 and the finite state machine returns to state 0. state 2: equalizer training the finite state machine remains in state 1 until the mse of the equalized training sequence falls between two specific threshold values. it should be noted that in state 1, the back-end section of the TDA8961 is continuously reset to make sure that after its demodulator has locked onto a signal, the trellis decoder and the following sections begin processing at the start of the next complete data field. the value of i 2 c-bus bit mse can be used for applications such as antenna pointing. state 3: normal operation normally the finite state machine remains in state 2 unless a synchronization error occurs. if the mse of the equalized training sequence exceeds 100 ms, the equalizer is reset for one symbol period and the adaptation process restarts. if the demodulator synchronization and equalization are both locked, pin eqlockindic goes high and i 2 c-bus bit lock_indicator is set to 11 (see table 16). the filtered output signal is then routed to the ntsc co-channel interference filter. ntsc co-channel interference ?lter the ntsc co-channel interference filter uses patented philips technology making its performance considerably better than the atsc specified comb filter. the filter can be bypassed by setting i 2 c-bus bit flt_bypass (see table 13).
2000 may 19 13 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 transport stream interface i ntroduction the transport stream interface performs the following functions: buffers the data from the reed solomon decoder and de-randomizer section inserts the mpeg sync byte at the start of every packet indicates error conditions using a transport_error_indicator bit in the packet header and the error signal output pdoerr. outputs either a serial or a parallel output format. p inning the functions of the transport stream interface outputs are summarized in table 3. it should be noted that different source decoder devices may have different uses for the pdoerr output; its polarity is programmable using i 2 c-bus bit fpbp (see table 14). p arallel output format figure 5 shows the timing diagram for the parallel output format. the pdosync signal indicates the occurrence of the sync byte in the packet and is only high for one clock period. the polarity of the pdoval and pdoerr signals is programmable via i 2 c-bus bits fdvp and fpbp respectively; fig.5 shows their default polarities. the pdoval signal is active for the duration of the 188 bytes of the transport stream packet. when the 188 bytes have been transferred, the pdoval signal goes low for at least ten pdoclk cycles during which, when used with dvb devices, the parity bytes are transferred; when used with non-dvb devices, zeroed parity bytes and field sync data are transferred. the period when the pdoval signal is low can vary, but will be a minimum of ten pdoclk cycles. due to the averaging operation of the fifo, the number of parity bytes transferred can vary slightly. the pdoclk signal runs continuously and is not affected by a reset. in parallel output format, it has a frequency of 3 mhz. when the TDA8961 is trying to acquire a channel, the pdoerr signal goes high (i 2 c-bus bit fpbp = 1). if this occurs, the pdoval signal stays low. s erial output format figure 6 shows the timing diagram for the serial output format. the lsb of the 8-bit pdo data bus is used to output the mpeg-2 transport stream packets. the pdosync signal indicates the occurrence of the sync byte in the packet and is only high during 8 pdoclk cycles. the polarity of the pdoval and pdoerr signals is programmable via i 2 c-bus bits fdvp and fpbp respectively; fig.6 shows their default polarities. the pdoval signal is active for the duration of the 188 bytes of the transport stream packet. when the 188 bytes have been transferred, the pdoval signal goes low for a period corresponding to the duration of the parity and field sync information. figure 6 shows the pdoerr signal is high for the whole packet length indicating that the packet contains errors. the pdoclk signal has a frequency of 27 mhz. table 3 transport stream interface outputs all pins are 3-state outputs. note 1. in serial output format, only pin pdo0 (lsb) is used to output the data. symbol function pdoclk clock signal for mpeg-2 packet data bytes (parallel and serial) pdoval indicates a valid data signal pdo7 to pdo0 packet data bits 7 to 0 (8-bit wide output bus) (1) pdosync indicates the start of a packet; goes high at the start of a packet and stays high during the ?rst byte, otherwise known as the sync byte pdoerr indicates packet error; goes high (i 2 c-bus bit fpbp = 1) for every packet (188 bytes) in which the reed solomon decoder found more errors than it could correct
2000 may 19 14 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 handbook, full pagewidth mgu090 20 (1) (3) (3) 1 2 186 187 (2) (2) (2) (2) (1) 1 pdoclk pdosync pdoval pdoerr pdo7 to pdo0 fig.5 parallel output format. (1) sync byte. (2) parity byte; contents set to 00h. (3) the polarity of these signals is programmable. handbook, full pagewidth sync byte (47h) byte 1 byte 187 msb 65 0 76 0 7 0 lsb 76 07 mgu091 (2) (1) (2) pdoclk pdo0 pdosync pdoval pdoerr fig.6 serial output format. (1) sync byte. (2) the polarity of these signals is programmable.
2000 may 19 15 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 s ync byte and transport stream error indicator figure 7 shows the structure of the so-called transport stream packet header of which only the first two bytes are significant to the TDA8961. the first byte in each header is the sync byte which must have the same value for all packets in accordance with the mpeg-2 standard specification. the TDA8961 sets the sync byte for each outgoing transport stream packet to 47h. the msb of the second byte in the header is the transport_error_indicator bit. it is asserted when the reed solomon decoder is unable to correct all errors in the transport stream packet and indicates that the packet contains invalid data. to perform bit error rate (ber) measurements, the external channel decoder generates a pseudo-random bit sequence (prbs) in the last 187 bytes of each transport stream packet.the same prbs signal is generated within the ber tester which compares it with the prbs in each transport packet and records any mismatch as an error. it should be noted that during ber measurements, the TDA8961 must not be allowed to set the transport_error_indicator bit. this option is possible using i 2 c-bus bit ftei (see table 14). if bit ftei is not set, the transport error interface bit is not allowed to indicate an error. if bit ftei is set, the reed solomon decoder is allowed to set the transport_error_indicator bit according to the result of the error correction process. this is the default setting. s erial transport stream input the TDA8961 can be used with another channel decoder without requiring the transport stream outputs from either decoder to be selected by an external switch. this configuration requires the serial transport stream output from the other channel decoder to be connected to the serial transport stream input of the TDA8961. when the system requires the transport stream from the other channel decoder, the TDA8961 internally connects pdierr to pdoerr, pdival to pdoval, pdiclk to pdoclk, pdisync to pdosync and pdi0 to pdo0 allowing the transport stream from the other channel decoder to pass through the TDA8961. this pass-through mode is enabled by setting the value of i 2 c-bus tsmode bits to 11 (see table 14). itu656 bypass mode figure 1 shows the tuner output connected to the tda8980 which processes the if and then outputs an 8-bit wide mpeg-2 transport stream to the TDA8961 where it is further processed before it is output to the video processor. this arrangement allows one system to receive both analog and digital broadcasts. when analog signals are received, the tda8980 supplies an itu656 format video stream to the TDA8961 input interface comprising pins adin9 to adin0 and adclk. the itu656 format uses 8-bit data and a 27 mhz clock signal. handbook, full pagewidth mgr605 payload (if present) adaptation field (if present) 0 0 msb sync byte transport_error_indicator transport packet header 1st byte 4th byte 1 0 0 0 1 1 1 lsb 188 bytes fig.7 transport packet header structure.
2000 may 19 16 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 pins pdo0 to pdo7 and pdoclk are normally part of the transport stream output interface. the signals to these pins are normally routed via an internal multiplexer. however, in the itu656 bypass mode, these pins connect directly to the lower 8 bits of adin9 to adin0 and adclk. in this mode, pdosync and pdoval are kept low and the polarity of pdoerr depends on the setting of i 2 c-bus bit fpbp. if required, these transport stream interface outputs can be forced to 3-state mode by making i 2 c-bus bit tso = 0 (see table 14). itu656 bypass mode is enabled by setting the i 2 c-bus tsmode bits to 10. s egment error counter the TDA8961 transport stream output interface is able to calculate the segment error, or packet error, rate (ser) over a certain time period. the time period can be set to either 1, 4, 8 or 16 seconds by the i 2 c-bus bits sertm (see table 14). the ic counts any packet errors occurring in the set time period. at the end of the time period, the 16-bit value representing the counted number of packet errors can be read via i 2 c-bus bit ser (see table 19). after a reset, the register value is set to 12935 (3287h) which is equivalent to an infinite ser. the TDA8961 is able to automatically reset itself when the ser exceeds a preset threshold value. the ser threshold is a 14-bit value programmable in the range 3 to 13000 represented by i 2 c-bus bits ser_thres (see table 14). it should be noted that the time period set by the sertm bits should be long enough to allow this threshold to be reached. this reset function is enabled by setting i 2 c-bus bit ser_rst (see table 14). the reset function is disabled by default. boundary scan interface the TDA8961 tap conforms to the ieee 1149.1 (jtag) standard. it is used for board-level testing and for internally testing integrated circuits. the jtag standard defines the on-chip test logic which comprises an instruction register, a group of test data registers including a bypass register and a boundary scan register, four dedicated pins comprising the tap, and a tap controller. e xternal interface the tap external interface has five pins whose functions are described in table 4. table 4 tap external interface i 2 c-bus interface the i 2 c-bus interface writes control information to, and reads low-speed diagnostic information from the TDA8961. the key features of the i 2 c-bus interface are: i 2 c-bus data rate of up to 400 kbits/s support for only 7-bit addressing and the ability to externally modify the slave address. a typical system using the i 2 c-bus interface is shown in fig.8. the TDA8961 is acting as a slave and is connected to a master via the i 2 c-bus lines scl and sda. it should be noted that the scl and sda lines are connected to separate pull-up resistors. signal description tms test mode select input tck test clock signal input tdi test data input tdo test data output trst test asynchronous reset input handbook, halfpage mgu089 TDA8961 i 2 c-bus master v dd r pu scl sda r pu fig.8 typical i 2 c system implementation.
2000 may 19 17 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 e xternal interface the i 2 c-bus external interface has three pins whose functions are described in table 5. table 5 i 2 c-bus external interface the TDA8961 i/o and i 2 c-bus signals range between ground and 3.3 v. systems that have devices which operate at different supply voltages may require special circuitry to allow these devices to communicate and to be controlled. circuit requirements are described in application report an97055 (issued aug. 04, 1997) available from philips semiconductors. a ddressing the device the TDA8961 must be addressed by its 7-bit (a6-a0) slave address sent via the system i 2 c-bus in accordance with the correct protocols, and with bit r/ w set to either 1 (write data) or 0 (read data). the slave address of the TDA8961 is given in table 6. bits a6 to a2 are preset, but bits a1 and a0 can be set via their corresponding external pins. table 6 TDA8961 slave address a write operation is shown in fig.9. the master transmitter sends a start condition followed by the 7-bit slave address which is followed by bit r/ w set to 0. the slave receiver (TDA8961) responds by sending an acknowledge. the master then sends write data starting at address zero. if the master sends more than one byte of write data, the TDA8961 automatically increments to the next address. the TDA8961 sends an acknowledge after it receives each byte. if the TDA8961 does not acknowledge the data transfer and/or the master sends a stop condition, the data transfer stops. it should be noted that the TDA8961 does not support i 2 c-bus sub-addressing. therefore, each i 2 c-bus transfer starting with the transmission of the slave address and bit r/ w, starts at address zero. a read operation is shown in fig.10. the master transmitter sends a start condition followed by the 7-bit slave address which is followed by bit r/ w set to 1. the slave receiver (TDA8961) responds by sending an acknowledge and the value at address zero. the master responds by sending an acknowledge. if the master follows the acknowledge with a stop condition, the data transfer stops, otherwise the slave is allowed to transfer more bytes. the slave TDA8961 automatically increments to the next address of read data to be sent to the master. signal description sda i 2 c-bus serial data input/output scl i 2 c-bus clock input a0 i 2 c-bus slave address input bit 0 a1 i 2 c-bus slave address input bit 1 a6 a5 a4 a3 a2 a1 a0 r/ w 00011a1a00=write 1 = read
2000 may 19 18 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 handbook, full pagewidth mgr607 s a data a (8) data p slave address (1)(2) (1)(3) (4)(5) (1) (4)(5) (4)(5)(6) (1) (1)(7) (1) r/w a/a fig.9 master transmitter addressing a slave receiver with a 7-bit address (write mode). (1) from master to slave (2) s = start condition (3) logic 0 (write) (4) from slave to master (5) a = acknowledge (sda low) (6) a = not acknowledge (sda high) (7) p = stop condition (8) data transferred (n bytes + acknowledge). handbook, full pagewidth mgr608 s a data a (8) data p slave address (1)(2) (1)(3) (4)(5) (4) (1)(5) (1)(6) (4) (1)(7) (1) r/w a fig.10 master transmitter addressing a slave receiver with a 7-bit address (read mode). (1) from master to slave. (2) s = start condition. (3) logic 1 (read). (4) from slave to master. (5) a = acknowledge (sda low). (6) a = not acknowledge (sda high). (7) p = stop condition. (8) data transferred (n bytes + acknowledge).
2000 may 19 19 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... i 2 c-bus register map table 7 i 2 c-bus write register overview function address (hex) d7 d6 d5 d4 d3 d2 d1 d0 general settings 00 eq_rst_ disable eq_freeze eq_reset be_reset gnrl_reset initial_ reset 01 agc_reset cr_reset tr_reset sr_reset 02 03 04 src 05 ad_fmt agc/ carrier recovery 06 agc_ samples agc_tr_low 07 agc_dir cr_inv 08 09 0a 0b 0c 0d 0e 0f 10 equalizer 11 mse_thr_1[15 to 8] 12 mse_thr_1[7 to 0] 13 mse_thr_2[15 to 8] 14 mse_thr_2[7 to 0] 15 16 17 18 19 1a
2000 may 19 20 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c ntsc co-channel interference ?lter 2d flt_bypass 2e 2f transport stream interface 30 ftei fpbp fdvp tso pmsm 31 ser_rst tsmode sertm 32 ser_thres[13 to 8] 32 ser_thres[7 to 0] 33 34 function address (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 may 19 21 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 table 8 general settings (write) notes 1. operating modes and control parameters of all sections in the TDA8961 are not affected. 2. operating modes and control parameters of all sections in the TDA8961 are reset to their initial values. table 9 sample rate converter settings (write) table 10 agc settings (write) bit name bit value description initial_reset 0 normal operation (default) 1 initial reset; note 1 gnrl_reset 0 normal operation (default) 1 general reset; note 2 be_reset 0 normal operation (default) 1 backend reset eq_reset 0 normal operation (default) 1 equalizer reset eq_freeze 0 normal operation (default) 1 equalizer adaptation freeze eq_rst_disable 0 normal operation (default) 1 equalizer reset disable fe_rst_disable 0 normal operation (default) 1 front-end reset disable sr_reset 0 normal operation (default) 1 reset sync recovery section agc_reset 0 normal operation (default) 1 reset input agc tr_reset 0 normal operation (default) 1 reset the timing recovery cr_reset 0 normal operation (default) 1 carrier recovery reset enable bit name bit value description ad_fmt 0 twos complement 1 binary (default) bit name bit value description agc_samples 0 average over 64 samples (default) 1 average over 256 samples agc_dir 0 agc operation compatible with tda8980 (default) 1 agc operation compatible with tda9819/9829 agc_tr_low - agc threshold value
2000 may 19 22 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 table 11 carrier recovery settings (write) table 12 equalizer settings (write) table 13 ntsc co-channel interference ?lter settings (write) table 14 transport stream interface settings (write) bit name bit value description cr_inv 0 selects non-inverted spectrum; carrier at lower band-edge 1 selects inverted spectrum; carrier at higher band-edge (default) bit name bit value description mse_thr_1 - mse loss-of-convergence threshold value 1 mse_thr_2 - mse loss-of-convergence threshold value 2 bit name bit value description flt_bypass 0 normal operation (default) 1 bypass ntsc co-channel interference ?lter bit name bit value description pmsm 0 parallel format (default) 1 serial format tso 0 transport stream outputs in 3-state mode 1 transport stream outputs active (default) fdvp 0 polarity of pdoval is low during the packet length of 188 data bytes 1 polarity of pdoval is high during the packet length of 188 data bytes (default) fpbp 0 polarity of pdoerr goes low if block cannot be corrected 1 polarity of pdoerr goes high if block cannot be corrected (default) ftei 0 transport_error_indicator bit is not allowed to indicate any errors detected in the transport stream 1 transport_error_indicator bit is allowed to indicate errors in the transport stream which could not be corrected by the reed solomon decoder (default) tsmode 00 normal operation (default) 01 reserved 10 itu656 bypass mode 11 serialized transport input (pass-through mode) sertm 00 ser is calculated over a 1 second period (default) 01 ser is calculated over a 4 second period 10 ser is calculated over a 8 second period 11 ser is calculated over a 16 second period ser_thres ser threshold value (used if ser_rst is set to 1) ser_rst 0 normal operation (default) 1 TDA8961 is reset when the ser exceeds 2.5
2000 may 19 23 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 table 15 i 2 c-bus read registers overview note 1. this register allows the type and version of the TDA8961 to be read by the controlling host. the type[3 to 0] field contains 1h corresponding to the TDA8961. the version[3 to 0] field contains eh corresponding to the TDA8961 version n1e. philips semiconductors reserves the right to change the values in this register for future versions of the TDA8961. table 16 general (read) table 17 carrier recovery (read) table 18 equalizer (read) function address (hex) d7 d6 d5 d4 d3 d2 d1 d0 basic operation 00 lock_i ndicat or s tat e carrier recovery 01 cr_offset[7 to 0] 02 03 equalizer 04 mse[15 to 8] 05 mse[7 to 0] 06 07 08 09 0a transport stream interface 0b ser[15 to 8] 0c ser[7 to 0] ic version (1) 0d type[3 to 0] version[3 to 0] bit name bit value description state 01 state 1 (channel acquisition) 10 state 2 (equalizer training) 11 state 3 (normal operation) lock_indicator 01 channel acquisition: no synchronization; equalization locked 10 equalizer training: synchronization locked; no equalization 11 normal operation: synchronization locked; equalization locked bit name bit value description cr_offset - carrier recovery offset value bit name bit value description mse - equalizer mean square error value
2000 may 19 24 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 table 19 transport stream interface (read) table 20 TDA8961 version (read) limiting values in accordance with the absolute maximum rating system (iec 60134) notes 1. human body model: 2000 v (typical); c = 100 pf; r = 1.5 k w ; 3 zaps positive and 3 zaps negative. 2. machine model: 200 v (typical); c = 200 pf; l = 0.5 m h; r = 10 w ; 3 zaps positive and 3 zaps negative. thermal characteristics quality specification in accordance with quality specification: snw-fq-611w . bit name bit value description ser - segment error rate value bit name bit value description type 0001 1h = TDA8961 version 1110 eh = TDA8961 version n1e symbol parameter conditions min. max. unit v dd supply voltage 3.0 3.6 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v i i dc current into any input - tbf ma i o dc current out of any output - tbf ma t j junction temperature 0 125 c t stg storage temperature -- c t amb ambient temperature - 20 +70 c p tot total power dissipation -- w v es electrostatic handling note 1 2000 4000 v note 2 200 400 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 43 k/w
2000 may 19 25 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 dc characteristics v dd = 3.3 v; v ss =0v; t amb =25 c; unless otherwise speci?ed; note 1. notes 1. all supply connections must be made to the same external power supply unit. 2. open drain output, determined by v dd via an external pull-up resistor. symbol parameter conditions min. typ. max. unit supply v dd supply voltage 2.7 3.3 3.6 v i dd supply current - 390 - ma inputs v il low-level input voltage -- 0.2v dd v v ih high-level input voltage 2.0 -- v i li input leakage current -- 1 m a c i input capacitance -- 25 pf outputs v ol low-level output voltage -- 0.4v dd v v oh high-level input voltage 0.85v dd -- v i ol low-level output current -- 4ma 3-state outputs (pins agcout, pdo7 to 0, pdoclk, pdosync, pdoval and pdoerr) i o(z) high-impedance output current -- 1 m a c o(z) high-impedance output capacitance -- 25 pf i 2 c-bus (pins sda and scl) v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.5 v v ol low-level output voltage 0 - 0.4 v v oh high-level output voltage note 2 -- v dd v i ol low-level output current v ol = 0.4 v 3 -- ma i l leakage current v i =v ss or v dd -- 10 m a c i input capacitance v i =v ss -- 8pf
2000 may 19 26 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 ac characteristics v dd = 3.3 v; v ss =0v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit system clock (pin xtali) f clk(sys) system clock frequency note 1 - 12 - mhz d clk(sys) system clock duty factor note 1 - 50 - % a/d interface (pins adin[9 to 0] and adclk); see fig.11 t su(a/d) a/d interface set-up time 5 -- ns t h(a/d) a/d interface hold time 5 -- ns t cy(adclk) adclk cycle time 27.8 -- ns transport stream interface (pins pdoclk, pdo[7 to 0], pdosync, pdoerr and pdoval) t pdoclkl(par) transport stream interface pdoclk low time; parallel format notes 2 and 3 166.7 -- ns t pdoclkh(par) transport stream interface pdoclk high time; parallel format notes 2 and 3 166.7 -- ns t cy(pdoclk)(par) transport stream interface pdoclk cycle time; parallel format notes 2 and 3 333.3 -- ns t pdovalh(par) transport stream interface pdoval high time; parallel format notes 3 and 4 62666.7 -- ns t pdovall(par) transport stream interface pdoval low time; parallel format note 3 --- ns ? t d(o)(par) ? delay between transport stream interface outputs pdo to pdoval, pdoerr and pdosync; parallel format note 3 0 -- ns t pdoclkl(ser) transport stream interface pdoclk low time; serial format notes 5 and 6 18.5 -- ns t pdoclkh(ser) transport stream interface pdoclk high time; serial format notes 5 and 6 18.5 -- ns t cy(pdoclk)(ser) transport stream interface pdoclk cycle time; serial format notes 5 and 6 37.0 -- ns t pdosynch(ser) transport stream interface pdosync high time; serial format note 5 296.3 -- ns t pdovalh(ser) transport stream interface pdoval high; serial format notes 5 and 7 55703.7 -- ns t pdovall(ser) transport stream interface pdoval low; serial format note 5 --- ns ? t d(o)(ser) ? delay between transport stream interface outputs pdo to pdoval, pdoerr and pdosync; serial format note 5 0 -- ns
2000 may 19 27 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 notes 1. the system clock signal is supplied by either an external 12 mhz crystal or another device such as the tda8980 generating a stable 12 mhz clock signal. 2. when used for parallel format, the frequency of pdoclk is 3 mhz. 3. see the timing measurement conditions in fig.12. 4. this is calculated by multiplying 188 bytes (the length of a packet) by the pdoclk clock cycle period. 5. see the timing measurement conditions in fig.13. 6. when used for serial format, the frequency of pdoclk is 27 mhz. 7. this is calculated by multiplying 188 bytes (the length of a packet) by the pdoclk clock cycle period, multiplied by 8. 8. c b = total capacitance of one bus line in pf. i 2 c-bus (pins sda and scl); see fig.15 f scl scl clock frequency 0 - 400 khz t buf bus free time between a stop and start condition 1.3 -- ms t hd;sta hold time for a repeated start condition; after this period the ?rst clock pulse is generated 0.6 -- ms t low low period of the scl clock 1.3 -- ms t high high period of the scl clock 0.6 -- ms t su;sta set-up time for a repeated start condition 0.6 -- ms t su;sto set-up time for stop condition 0.6 -- ms t hd;dat data hold time 0 - 0.9 ms t su;dat data set-up time 100 -- ns t sp pulse width of spikes which must be suppressed by the input ?lter tbf - tbf ns t r rise time of both sda and scl signals note 8 20 + 0.1c b - 300 ns t f fall time of both sda and scl signals 20 + 0.1c b - 300 ns c b capacitive load for each bus line -- 400 pf jtag interface (pins tdo, tdi, tck, tms and trst); see fig.14 t d(tck-tdo) pin tck to tdo valid delay 2 - 10 ns t su(i)(tck) input set-up time to tck 10 -- ns t h(i)(tck) input hold time from tck 2 -- ns reset (pin rst_an) t su(po)l power-on set-up time low 23 -- ns symbol parameter conditions min. typ. max. unit
2000 may 19 28 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 handbook, full pagewidth mgu092 adclk adin9 to adin0 t cy(adclk) t su(a/d) t h(a/d) valid fig.11 a/d interface timing. handbook, full pagewidth mgu093 pdoclk t pdoclkl(par) t pdoclkh(par) t pdovalh(par) | t d(o)(par) | t pdovall(par) t cy(pdoclk)(par) 47h pdosync pdoval pdoerr pdo7 to pdo0 fig.12 transport stream interface timing (parallel output format).
2000 may 19 29 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 handbook, full pagewidth mgu094 0 pdo0 pdoerr pdoval pdosync pdoclk 1001111 t pdoclkl(ser) t pdoclkh(ser) t pdovalh(ser) | t d(o)(ser) | t pdovall(ser) t pdosynch(ser) t cy(pdoclk)(ser) fig.13 transport stream interface timing (serial output format). handbook, full pagewidth mgu095 tck tdo t su(i)(tck) t h(i)(tck) t d(tck-tdo) valid fig.14 jtag i/o timing.
2000 may 19 30 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.15 i 2 c-bus timing diagram. p = stop condition. s = start condition. sr = repeated start condition.
2000 may 19 31 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 14.1 13.9 0.8 1.95 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-2 mo-112 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p detail x l (a ) 3 b 24 c b p e h a 2 d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y d h v m b w m w m 97-08-01 99-12-27 0 5 10 mm scale qfp80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot318-2 a max. 3.2
2000 may 19 32 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 may 19 33 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 may 19 34 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2000 may 19 35 philips semiconductors objective speci?cation atsc digital terrestrial tv demodulator/decoder TDA8961 notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/01/pp 36 date of release: 2000 may 19 document order number: 9397 750 06769

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